The present invention relates to a technology for preventing a delay value of a delay circuit whose function is to adjust a sensing margin of a bit line sense amp (BLSA) in a semiconductor memory device according to variations of process, voltage, and temperature (PVT) conditions in a chip. The delay circuit of the invention can be applied to a variety of integrated circuits (ICs) and semiconductor devices as well as semiconductor memory devices.
FIG. 1 is a circuit diagram illustrating a core region of a conventional semiconductor memory device, and FIG. 2 is a timing diagram illustrating the operation of a core region of a semiconductor device. The operation of a core region of a semiconductor memory device will be described with reference to FIGS. 1 and 2.
Once an active command is inputted, a word line is enabled (i.e., WL=‘high’) and a transistor 101 is turned on. Therefore, data stored in a cell capacitor 102 may experience a charge-sharing phenomenon with respect to a bit line BL. Accordingly, nodes SA and SAB have a predetermined potential difference ΔV and, a bit line sense amp (BLSA) 103 is enabled after a predetermined delay (i.e., a sensing margin shown in FIG. 2) elapses. Thus, the nodes SA(BL) and SAB(BLB) have a predetermined potential difference between an effective ground VSS and a core operating voltage VCORE (it is assumed that data of 0 is stored in a cell capacitor).
Here, a time difference between when the word line WL is enabled and when the bit line sense amp (BLSA) 103 is enabled is called a sensing margin. If the time difference becomes shortened and the bit line sense amp (BLSA) 103 is enabled without adequate ΔV, data cannot be amplified properly. Consequently, a read failure occurs. Additionally, if the sensing margin exceeds a predetermined level, time for performing a read operation is increased such that tRCD (an important parameter of a memory device) also is increased.
Accordingly, the minimum sensing margin is secured under the PVT conditions in order for a memory device to operate stably and fast.
Signals BISH and BISL of FIG. 1 are signals for connecting and disconnecting the bit lines BL and BLB of a cell array with the bit lines SA and SAB of the bit line sense amp (BLSA) 103. A signal BLEQ is a bit line equalize signal for equalizing the bit lines BL and BLB during a precharge operation. The signal BLEQ is known to those skilled in the art. Thus, its detailed description will be omitted for conciseness.
FIG. 3 is a view illustrating a part for driving a word line and a sense amp in a conventional semiconductor memory device. As illustrated in FIG. 3, the conventional semiconductor memory device includes a word line driving circuit 310 for driving a word line WL, and a sense amp driving circuit 330, a delay circuit 320, and the sense amp driving circuit 330.
Once an active command is inputted, a word line enable signal WLE is enabled. In response to the word line enable signal WLE, the word line driving circuit 310 enables the word line WL.
The word line enable signal WLE is also inputted to the delay circuit 320, and the delay circuit 320 delays the word line enable signal WLE by its delay value and then outputs the delayed sense amp enable signal SAE. The sense amp driving circuit 330 enables the bit line sense amp (BLSA) 103 of FIG. 1 in response to the sense amp enable signal SAE. The bit line sense amp (BLSA) 103 is enabled by supplying driving voltages RTO and SB.
The word line enable signal WLE for determining the timing of enabling the word line WL is delayed by the delay circuit 320 and thus becomes the sense amp enable signal SAE for determining the timing of enabling the bit line sense amp (BLSA) 103. A time difference between enabling the word line WL and enabling the bit line sense amp (BLSA) 103 is the sensing margin of the bit line sense amp (BLSA) 103. As a result, a delay value of the delay circuit 320 becomes the sensing margin of the bit line sense amp (BLSA) 103.
Accordingly, the delay value of the delay circuit 320 corresponds to a very important factor during a particular operation of a core region of a memory device.
FIG. 4 is a circuit diagram illustrating a detail structure of the delay circuit 320 of FIG. 3. As illustrated in FIG. 4, the conventional delay circuit 320 delays a word line enable signal WLE through a plurality of capacitors 450 to 480 disposed between a plurality of inverters 410 and 440.
In relation to the above-mentioned operation, the inverters 410 to 440 invert an input signal (i.e., the word line enable signal WLE), and capacitors 450 to 480 are discharged and charged by a current flowing through transistors and resistors 411, 421, 431 and 441 in the inverters 410 and 440. The capacitors 450 to 480 are charged and discharged and also delay a time for transmitting the word line enable signal WLE. Accordingly, the word line enable signal WLE inputted to the delay circuit 320 is delayed by the inverters 410 to 440 and the capacitors 450 to 480, and then becomes a sense amp enable signal SAE. For reference, N+ active resistors are typically used as the resistors 411, 421, 431 and 441.
A delay time of the delay circuit 320 is dependent upon a time for charging and discharging the capacitors 450 to 480. Also, the time for charging and discharging the capacitors 450 to 480 is dependent upon a current flowing through the capacitors 450 to 480. The current flowing through the capacitors 450 to 480 may vary according to the resistance values of the transistors and the N+ active resistors 411, 421, 431 and 441, which constitute the inverters 410 to 440.
If a fabrication line of a semiconductor memory device is changed or its fabrication process is unstable, the resistance values of the transistors and the N+ active resistors 411, 421, 431 and 441, which constitute the inverters 410 to 440, are changed. Additionally, the changed resistance values affect a time for charging and discharging the capacitors 450 to 480. That is, a delay value of the delay circuit 320 having a conventional structure may vary greatly if the fabrication line is altered or its fabrication process is performed with no predictable pattern.
FIG. 5 is a view illustrating a change of a sensing margin according to a design of the delay circuit 320. A reference letter (A) represents a case in which a delay value of the delay circuit 320 is designed with a relatively small value, and a reference letter (B) represents a case in which a delay value of the delay circuit 320 is designed with a relatively large value. A reference letter FF represents a condition of when a delay value of the delay circuit 320 is the smallest because a fabrication process has a fast characteristic and a power supply voltage VDD is high. A reference letter NOM is represents a condition of when a delay of the delay circuit 320 is average because a fabrication process has an average characteristic and a power supply voltage VDD is average. A reference letter SS represents a condition of when a delay value of the delay circuit 320 is the largest because a process has a slow characteristic and a power supply voltage VDD is low.
First, let's examine the case (A). According to the conventional delay circuit 320, a delay change varies greatly according to changes of a fabrication process and a power supply voltage, as mentioned above. Therefore, the fabrication process is performed being biased toward a direction where the fabrication process is performed at a faster speed, and a delay value of the delay circuit 320 may become smaller than the minimum sensing margin SM_MIN in the case FF. If a delay value of the delay circuit 320 becomes smaller than the minimum sensing margin SM_MIN, the bit line sense amp (BLSA) 130 starts an amplification process when charge sharing is not completely finished. This causes a read failure.
To resolve the limitation of the case (A), let's examine the case (B) in which a delay value of the delay circuit 320 is designed with a large value.
In the case (B), because a delay value of the delay circuit 320 is designed with a large value, the delay circuit 320 has a larger delay value than the minimum sensing margin SM_MIN even under the condition FF. However, under the condition SS (i.e., the delay value of the delay circuit is largest), a delay value of the delay circuit 320 increases excessively such that an operating speed of a memory device can deteriorate.
That is, if a delay value of the delay circuit 320 is changed according to the conditions, the minimum sensing margin SM_MIN may not be obtained (i.e., the case A) or an operating speed of a memory device can deteriorate (i.e., the case B), leading to undesirable operation.
Therefore, a delay circuit capable of having a predetermined delay value constantly even when conditions are changed is desirable.